PIC16F77T-I/ML【PDF 56/104 页】IC MCU FLASH 8KX14 A/D 44QFN

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Sheet目录3882

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Micrel, Inc.

KSZ8851-16MLLJ

March 2010

M9999-030210-1.0

On-Chip Bus Control Register (0x20 – 0x21): OBCR

This register controls the on-chip bus clock speed for the KSZ8851-16MLLJ. The default of the on-chip bus clock speed is

125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best

performance.

Bit

Default Value

R/W

Description

15-7

Reserved.

Output Pin Drive Strength

Bi-directional or output pad drive strength selection.

0: 8 mA; 1: 16 mA

5-3

Reserved.

On-Chip Bus Clock Selection

0: 125MHz (default setting is divided by 1, Bit[1:0]=00)

1: NA (reserved)

1-0

0x0

On-Chip Bus Clock Divider Selection

00: Divided by 1; 01: Divided by 2; 10: Divided by 3; 11: NA (reserved).

For example to contol the bus clock speed as below:

If Bit 2 = 0 and this value is set 00 to select 125 MHz.

If Bit 2 = 0 and this value is set 01 to select 62.5 MHz.

EEPROM Control Register (0x22 – 0x23): EEPCR

To support an external EEPROM, pulled-up the EED_IO pin to High; otherwise, it is pulled-down to Low. If an external

EEPROM is not used, the software programs the host MAC address. If an EEPROM is used in the design, the chip host

MAC address is loaded from the EEPROM immediately after reset. The KSZ8851-16MLLJ allows the software to access

(read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the

EEPROM Software Access bit is set.

Bit

Default Value

R/W

Description

15-6

Reserved.

EESRWA EEPROM Software Read or Write Access

0: software read enable to access EEPROM when software access enabled (bit4=1)

1: software write enable to access EEPROM when software access enabled (bit4=1).

EESA EEPROM Software Access

1: enable software to access EEPROM through bit 3 to bit 0.

0: disable software to access EEPROM.

EESB EEPROM Status Bit

Data Receive from EEPROM. This bit directly reads the EED_IO pin.

2-0

0x0

EECB EEPROM Control Bits

Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EED_IO pin.

Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.

Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin.

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